4-bit synchronous decade counter with synchronous reset

DESCRIPTION The HEF40162B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

文件：166.73 Kbytes 页数：10 Pages

PHI

PHI

4-bit synchronous decade counter with synchronous reset

DESCRIPTION The HEF40162B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

文件：166.73 Kbytes 页数：10 Pages

PHI

PHI

4-bit synchronous decade counter with synchronous reset

DESCRIPTION The HEF40162B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

文件：166.73 Kbytes 页数：10 Pages

PHI

PHI

4-bit synchronous decade counter with synchronous reset

DESCRIPTION The HEF40162B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

文件：166.73 Kbytes 页数：10 Pages

PHI

PHI