HDD128M72D18RPW-13B中文资料HANBIT数据手册PDF规格书

GENERAL DESCRIPTION

The HDD128M72D18RPW is a 128M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 64M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD128M72D18RPW is a DIMM( Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance mem ory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.

FEATURES

• Part Identification

HDD128M72D18RPW – 13A : 133MHz (CL=2)

HDD128M72D18RPW – 13B : 133MHz (CL=2.5)

HDD128M72D18RPW – 16B : 166MHz (CL=2.5)

• 1024MB(64Mx72) Registered DDR DIMM based on 64Mx8 DDR SDRAM

• 2.5V ± 0.2V VDD and VDDQ power supply

• Auto & self refresh capability (8K Cycles / 64ms)

• All input and output are compatible with SSTL_2 interface

• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

• MRS cycle with address key programs

- Latency (Access from column address) : 2, 2.5

- Burst length : 2, 4, 8

- Data scramble : Sequential & Interleave

• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

• The used device is 16M x 8bit x 4Banks DDR SDRAM