Octal D-type Transparent Latches with 3-state Outputs

Description The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high agai

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3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O

DESCRIPTION: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. FEATURES:

文件：68.7 Kbytes 页数：6 Pages

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3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O

DESCRIPTION: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. FEATURES:

文件：68.7 Kbytes 页数：6 Pages

IDT

3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O

DESCRIPTION: The LVC373A Octal transparent D-type latch is built using advanced dual metal CMOS technology. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. FEATURES:

文件：68.7 Kbytes 页数：6 Pages

IDT