Parallel-Load 8-bit Shift Register

Description The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded

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Parallel-Load 8-bit Shift Register

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Parallel-Load 8-bit Shift Register

文件：108.89 Kbytes 页数：10 Pages

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General-Purpose Logics

The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the • VCC = 2.0 V to 5.5 V operation\n• All outputs VO(Max.)= 5.5 V(@VCC = 0 V)\n• Typical VOH undershoot > 2.3 V(@VCC = 3.3 V, Ta = 25°C)\n• Ordering Information;

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