HD74LV138A中文资料日立数据手册PDF规格书

描述 Description

The HD74LV138A is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. The conditions at the binary-select inputs and the three enable inputs select one of eight input lines.

Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter.

特性 Features

• VCC = 2.0 V to 5.5 V operation

• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)

• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)