Octal D-type Transparent Latches (with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high a

文件：121.46 Kbytes 页数：9 Pages

RENESAS

瑞萨

Octal D-type Transparent Latches (with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high a

文件：121.46 Kbytes 页数：9 Pages

RENESAS

瑞萨

Octal D-type Transparent Latches (with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high a

文件：121.46 Kbytes 页数：9 Pages

RENESAS

瑞萨

Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS

文件：116.59 Kbytes 页数：5 Pages

INTEGRAL

Integral Corp.