8-bit Latch/Shift Register

Description The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. Features •

文件：57.47 Kbytes 页数：10 Pages

HitachiHitachi Semiconductor

日立日立公司

8-bit Latch / Shift Register

Description The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. Features •

文件：117.16 Kbytes 页数：10 Pages

RENESAS

瑞萨

8-bit Latch/Shift Register

Description\nThe HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. •  High Speed Operation: tpd(SCK to QH’) = 14 ns typ (CL= 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C);

HITACHI

日立

Standard IC>General-Purpose Logics>HD74HC Series

Renesas

瑞萨

8-bit Latch / Shift Register

Description The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. Features •

文件：117.16 Kbytes 页数：10 Pages

RENESAS

瑞萨

8-bit Latch / Shift Register

Description The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. Features •

文件：117.16 Kbytes 页数：10 Pages

RENESAS

瑞萨

8-bit Latch / Shift Register

Description The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. Features •

文件：117.16 Kbytes 页数：10 Pages

RENESAS

瑞萨

8-bit Latch / Shift Register

Description\nThe HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. •  High Speed Operation: tpd(SCK to QH’) = 14 ns typ (CL= 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C);

Renesas

瑞萨