BCD-to-Seven Segment Latch/Decoder/Driver

Description This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 output drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (Ph) controls the polarity of the

文件：118.94 Kbytes 页数：9 Pages

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瑞萨

BCD-to-Seven Segment Latch/Decoder/Driver

Features • High Speed Operation: tpd (A, B, C, D to a – g) = 33 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 μA max • Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C) • Ordering Informatio

文件：296.04 Kbytes 页数：11 Pages

RENESAS

瑞萨

BCD-to-Seven Segment Latch/Decoder/Driver

Description This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 output drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (Ph) controls the polarity of the

文件：118.94 Kbytes 页数：9 Pages

RENESAS

瑞萨

BCD-to-Seven Segment Latch/Decoder/Driver

Features • High Speed Operation: tpd (A, B, C, D to a – g) = 33 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 μA max • Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C) • Ordering Informatio

文件：296.04 Kbytes 页数：11 Pages

RENESAS

瑞萨

BCD-to-Seven Segment Latch/Decoder/Driver

Description This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 output drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (Ph) controls the polarity of the

文件：118.94 Kbytes 页数：9 Pages

RENESAS

瑞萨