7-stage Binary Counter

Description The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Features • High Speed Operation: tpd (Clock to Q1) = 14 ns

文件：91.59 Kbytes 页数：7 Pages

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7-stage Binary Counter

Description The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Features • High Speed Operation: tpd (Clock to Q1) = 14 ns

文件：91.59 Kbytes 页数：7 Pages

RENESAS

瑞萨

7-stage Binary Counter

Description The HD74HC4024 is a 7-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Features • High Speed Operation: tpd (Clock to Q1) = 14 ns

文件：91.59 Kbytes 页数：7 Pages

RENESAS

瑞萨

7 STAGE BINARY COUNTER

DESCRIPTION The M54/74HC4024 is a high speed CMOS 7-STAGE BINARY COUNTER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 13 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25° C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.) ■ OUTPUT

文件：246.62 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体