HD74HC393FPEL中文资料瑞萨数据手册PDF规格书

描述 Description

The HD74HC393 contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256 counter.

The HD74HC393 is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input. When clear is set high all four bitsof each counter are set to a low level. This enables count truncation and allows the implementation of divide-by-N counter configurations.

特性 Features

• High Speed Operation: tpd(A to QA) = 16 ns typ (CL= 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC= 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)