Octal D-Type Transparent Latches (3-State Outputs) Octal D-Type Transparent Latches (Inverted 3-State Outputs)

When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high l • High-Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF)\n• High Output Current: Fanout of 15 LSTTL Loads\n• Wide Operating Voltage: VCC = 2 to 6 V\n• Low Input Current: 1 µA max\n• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C);

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Octal D-type Transparent Latches (with 3-state outputs)

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Octal D-type Transparent Latches (with 3-state outputs)/Octal D-type Transparent Latches (with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again

文件：119.33 Kbytes 页数：10 Pages

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Octal D-type Transparent Latches (with 3-state outputs)

文件：163.47 Kbytes 页数：12 Pages

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Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS

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INTEGRAL

Integral Corp.