8-bit Addressable Latch

Description The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a common enable input (E), and a common clear input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to

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HITACHIHitachi Semiconductor

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8-bit Addressable Latch

Description The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a common enable input (E), and a common clear input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to

文件：104.66 Kbytes 页数：10 Pages

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8-bit Addressable Latch

HITACHI

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Standard IC>General-Purpose Logics>HD74HC Series

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瑞萨

8-bit Addressable Latch

Description The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a common enable input (E), and a common clear input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to

文件：104.66 Kbytes 页数：10 Pages

RENESAS

瑞萨

8-bit Addressable Latch

Description The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a common enable input (E), and a common clear input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to

文件：104.66 Kbytes 页数：10 Pages

RENESAS

瑞萨

8-bit Addressable Latch

Description The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a common enable input (E), and a common clear input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to

文件：104.66 Kbytes 页数：10 Pages

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瑞萨