HD74HC174中文资料日立数据手册PDF规格书

描述 Description

This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state.

特性 Features

• High Speed Operation: tpd(Clock to Q) = 15 ns typ (CL= 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC= 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)