Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will

文件：240.9 Kbytes 页数：10 Pages

RENESAS

瑞萨

Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will

文件：240.9 Kbytes 页数：10 Pages

RENESAS

瑞萨

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Output

文件：179.36 Kbytes 页数：5 Pages

INTEGRAL

Integral Corp.

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. • Output

文件：223.9 Kbytes 页数：6 Pages

IKSEMICON