8-bit Binary Programmable Counter with Synchronous Preset Enable

Description The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter o

文件：218.07 Kbytes 页数：14 Pages

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9 bit Level Shifter/Transceiver With 3 State Outputs

Description The HD151015 is an IC which consists of 9 bus transceivers (three state output) in a 24 pin package. Signals are transmitter from A to B when the direction control input (DiR) is at a high level, and from B to A when DiR is at a low level. When the enable input (G) is high, A and B ar

文件：80.24 Kbytes 页数：13 Pages

HITACHIHitachi Semiconductor

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9 bit Level Shifter/Transceiver With 3 State Outputs

Description The HD151015 is an IC which consists of 9 bus transceivers (three state output) in a 24 pin package. Signals are transmitter from A to B when the direction control input (DiR) is at a high level, and from B to A when DiR is at a low level. When the enable input (G) is high, A and B ar

文件：203.16 Kbytes 页数：11 Pages

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9 bit Level Shifter/Transceiver With 3 State Outputs

Description The HD151015 is an IC which consists of 9 bus transceivers (three state output) in a 24 pin package. Signals are transmitter from A to B when the direction control input (DiR) is at a high level, and from B to A when DiR is at a low level. When the enable input (G) is high, A and B ar

文件：203.16 Kbytes 页数：11 Pages

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9 bit Level Shifter/Transceiver With 3 State Outputs

文件：202.82 Kbytes 页数：11 Pages

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2.5 V PLL Clock Buffer for DDR Applicationjpeg

文件：193.77 Kbytes 页数：8 Pages

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2.5 V PLL Clock Buffer for DDR Application

文件：91.51 Kbytes 页数：13 Pages

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2.5 V PLL Clock Buffer for DDR Applicationjpeg

文件：193.77 Kbytes 页数：8 Pages

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2.5 V PLL Clock Buffer for DDR Application

文件：91.51 Kbytes 页数：13 Pages

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2.5 V PLL Clock Buffer for DDR Applicationjpeg

文件：193.77 Kbytes 页数：8 Pages

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