丝印：HCT161M；Package：SOIC；High-Speed CMOS Logic Presettable Counters

Features • ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset • ’HC163, ’HCT163 4-Bit Binary Counter, Synchronous Reset • Synchronous Counting and Loading • Two Count Enable Inputs for n-Bit Cascading • Look-Ahead Carry for High-Speed Counting • Fanout (Over Temperature Range) - Sta

文件：383.44 Kbytes 页数：20 Pages

TI

德州仪器

丝印：HCT161M；Package：SOIC；High-Speed CMOS Logic Presettable Counters

Features • ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset • ’HC163, ’HCT163 4-Bit Binary Counter, Synchronous Reset • Synchronous Counting and Loading • Two Count Enable Inputs for n-Bit Cascading • Look-Ahead Carry for High-Speed Counting • Fanout (Over Temperature Range) - Sta

文件：383.44 Kbytes 页数：20 Pages

TI

德州仪器

丝印：HCT161M；Package：SOIC；High-Speed CMOS Logic Presettable Counters

Features • ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset • ’HC163, ’HCT163 4-Bit Binary Counter, Synchronous Reset • Synchronous Counting and Loading • Two Count Enable Inputs for n-Bit Cascading • Look-Ahead Carry for High-Speed Counting • Fanout (Over Temperature Range) - Sta

文件：383.44 Kbytes 页数：20 Pages

TI

德州仪器

Radiation Hardened Synchronous Counter

Description The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous counter features asynchronous reset and look-ahead carry logic. The HCTS161AMS has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting

文件：115.77 Kbytes 页数：9 Pages

INTERSIL

Radiation Hardened Synchronous Counter

Features • 3 Micron Radiation Hardened CMOS SOS • Total Dose 200K RAD (Si) • Minimum LET for SEU Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity 1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latc

文件：396.42 Kbytes 页数：9 Pages

RENESAS

瑞萨

Radiation Hardened Synchronous Counter

Description The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous counter features asynchronous reset and look-ahead carry logic. The HCTS161AMS has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting

文件：115.77 Kbytes 页数：9 Pages

INTERSIL