HCC4541B中文资料意法半导体数据手册PDF规格书

DESCRIPTION

The HCC/HCF4541B Programmable Timer is composed of a 16-stage binary counter, an oscillator controlled by2 external resistorsand a capacitor, an output control logic and an automatic power-on reset circuit. The counter varies on positive-edge clock transation and it can be cleared by the MASTER RESET input. The output from this timer is the Q or Q output from the 8th, 13th, or 16th counter stage. The choice of the stage depends on the time select inputs A or B (see frequency selection table).

■ 16 STAGE BINARI COUNTER

■ LOW SYMMETRICAL OUTPUT RESISTANCE, TYPICALLY 100 OHM AT VDD = 15V

■ OSCILLATOR FREQUENCY RANGE : DC TO 100kHz

■ AUTO OR MASTER RESET DISABLES OSCILLATOR DURING RESET TO REDUCE POWER DISSIPATION

■ OPERATES WITH VERY SLOW CLOCK RISE AND FALL TIMES

■ BUILT-IN LOW-POWER RC OSCILLATOR

■ EXTERNAL CLOCK (applied to pin 3) CAN BE USED INSTEAD OF OSCILLATOR

■ OPERATES AS 2N FREQUENCY DIVIDER OR AS A SINGLE-TRANSITION TIMER

■ Q/Q SELECT PROVIDES OUTPUT LOGIC LEVEL FLEXIBILITY CAPABLE OF DRIVING SIX LOW POWER TTL LOADS, THREE LOW-POWER SCHOTTKY LOADS, PR SIX HTL LOADS OVER THE RATED TEMPERATURE RANGE

■ SYMMETRICAL OUTPUT CHARACTERISTICS

■ 100 TESTED FOR QUIESCENT CURRENT AT 20V

■ 5-10-15V PARAMETRIC RATINGS

■ MEETS ALL REQUIREMENTS OF JEDECTEN TATIVE STANDARD N 13A, ”STANDARD SPE CIFICATIONS FOR DESCRIPTION OF ’ B ’ SERIES CMOS DEVICES”