HC705C5GRSSLASHD中文资料恩XP数据手册PDF规格书

FEATURES

HC05 Core 40-pin DIP or 44-pin plastic-leaded chip carrier (PLCC) package On-Chip Oscillator with Crystal/Ceramic Resonator 5184 Bytes of User EPROM 176 Bytes of On-Chip RAM 128 Bytes of EEPROM EEPROM Low Voltage Program Inhibit (LVPI) enabled by LVPI bit in MOR register Hardware EEPROM Program Enable 16-Bit Timer COP Watchdog Timer controlled by the COP bit in the MOR register 32 Bidirectional I/O Lines Single-Chip Mode Boot Mode Power-Saving STOP and WAIT Modes Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger controlled by the IRQ bit in the MOR register Simple Serial Input/Output Port MSB/LSB controlled by the SIOP bit in the MOR register 10 mA Sink Capability on One 8-Bit Port