Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

General Description The HC2510C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM Features ● Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications ● Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specifi

文件：81.19 Kbytes 页数：6 Pages

Hynix

海力士

Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

SK hynix

海力士

Change to improved mold compound

文件：96.69 Kbytes 页数：4 Pages

AVAGO

安华高

Glass Passivated 3 Phase Bridge Rectifier

Features • Glass passivated chip, high reliability • Low forward voltage drop • Insulation voltage 2,500V • Small size and light weight • Small thermal resistance, high thermal conductivity and low temperature rise Applications • Power supply of DC equipment • Input rectifier for PWM con

文件：337.48 Kbytes 页数：3 Pages

MULTICOMP

易络盟

Low voltage dual channel H-bridge driver

文件：763.9 Kbytes 页数：9 Pages

HMSEMI

华之美半导体