HC2509C中文资料PDF规格书
HC2509C规格书详情
General Description
The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM.
Features
● Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
● Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2”
● Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
● No External RC Network Required
● External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input
● Separate Output Enable for Each Output Bank
● Operates at 3.3 V Vcc
● 125 MHz Maximum Frequency
● On-chip Series Damping Resistors
● Support Spread Spectrum Clock(SSC) Synthesizers
● ESD Protection Exceeds 3000 V per MIL-STD- 883, Method 3015 ; Exceeds 350 V Using Machine Model ( C = 200 pF, R = 0 )
● Latch-Up Performance Exceeds 400 mA per JESD 17
● Packaged in Plastic 24-Pin Thin Shrink SmallOutline Package
产品属性
- 型号:
HC2509C
- 制造商:
HYNIX
- 制造商全称:
Hynix Semiconductor
- 功能描述:
Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
TI |
2020+ |
SOP |
80000 |
只做自己库存,全新原装进口正品假一赔百,可开13%增 |
询价 | ||
TI/德州仪器 |
23+ |
SOP16 |
15000 |
全新原装现货,价格优势 |
询价 | ||
ST/意法 |
23+ |
SOP |
5200 |
原厂原装 |
询价 | ||
PANASONIC/松下 |
18+19+ |
NA |
880000 |
明嘉莱只做原装正品现货 |
询价 | ||
HYUNDAI |
99+ |
848 |
全新原装!优势库存热卖中! |
询价 | |||
HAR |
22+ |
SOP-16 |
3200 |
绝对原装自家现货!真实库存!欢迎来电! |
询价 | ||
TI |
20+ |
SOP16 |
2960 |
诚信交易大量库存现货 |
询价 | ||
ST/意法 |
SOP |
209709 |
一级代理原装正品,价格优势,支持实单! |
询价 | |||
TI |
23+ |
SOP20PIN |
65480 |
询价 | |||
ST |
2016+ |
SOP |
6528 |
只做原装正品现货!或订货 |
询价 |