BD1HC500EFJ-CE2

Marking：HC500；Package：HTSOP-J8；1ch High-side switch

Features ■Built-inovercurrentprotectioncircuit ■Built-inThermalShutDown(TSD) ■Built-inOpenLoadDetectioncircuit(WhenOutputis OFF) ■PossibilitytocontroldirectlyfromCMOSlogicIC ■Lowstandbycurrent ■Built-inUnderVoltageLockOutcircuit ■Built-indiagnostic(ST)out

BD1HCU50EFJ-CE2

Marking：HCU50；Package：HTSOP-J8；1ch High-side switch

Features ■Built-inovercurrentprotectioncircuit ■Built-inThermalShutDown(TSD) ■Built-inOpenLoadDetectioncircuit(WhenOutputis OFF) ■PossibilitytocontroldirectlyfromCMOSlogicIC ■Lowstandbycurrent ■Built-inUnderVoltageLockOutcircuit ■Built-indiagnostic(ST)out

BFN23

Marking：HCs；Package：SOT-23；PNP Silicon High-Voltage Transistor (Suitable for video output stages in TV sets and switching power supplies High breakdown voltage)

PNPSiliconHigh-VoltageTransistor ●SuitableforvideooutputstagesinTVsetsandswitchingpowersupplies ●Highbreakdownvoltage ●Lowcollector-emittersaturationvoltage ●Lowcapacitance ●Complementarytype:BFN22(NPN)

CD74HC109M

Marking：HC109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features •AsynchronousSetandReset •SchmittTriggerClockInputs •TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads •Wi

CD74HC109M96

Marking：HC109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features •AsynchronousSetandReset •SchmittTriggerClockInputs •TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads •Wi

CD74HC109M96.A

Marking：HC109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features •AsynchronousSetandReset •SchmittTriggerClockInputs •TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC •Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads •Wi

CD74HC112M96

Marking：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features •Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes •Asynchronoussetandreset •Complementaryoutputs •Bufferedinputs •TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ •Fanout(overtemperaturerange) –Standardoutput

CD74HC112MT

Marking：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features •Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes •Asynchronoussetandreset •Complementaryoutputs •Bufferedinputs •TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ •Fanout(overtemperaturerange) –Standardoutput

CD74HC112NS

Marking：HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features •Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes •Asynchronoussetandreset •Complementaryoutputs •Bufferedinputs •TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ •Fanout(overtemperaturerange) –Standardoutput

CD74HC112NSR

Marking：HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features •Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes •Asynchronoussetandreset •Complementaryoutputs •Bufferedinputs •TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ •Fanout(overtemperaturerange) –Standardoutput