H5TQ2G63GFR-PBL中文资料海力士数据手册PDF规格书

FEATURES

• VDD=VDDQ=1.5V +/- 0.075V

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• On chip DLL align DQ, DQS and DQS transition with CK

transition

• DM masks write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data,

data strobes and data masks latched on the

rising edges of the clock

• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13

and 14 supported

• Programmable additive latency 0, CL-1, and CL-2

supported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8

9 and 10

• Programmable burst length 4/8 with both nibble

sequential and interleave mode

• BL switch on the fly

• 8banks

• Average Refresh Cycle (Tcase 0 oC~ 95 oC)

- 7.8 μs at 0oC ~ 85 oC

- 3.9 μs at 85oC ~ 95 oC

Commercial Temperature( 0oC ~ 95 oC)

Industrial Temperature( -40oC ~ 95 oC)

• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)

• Driver strength selected by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported

• ZQ calibration supported

• TDQS (Termination Data Strobe) supported (x8 only)

• Write Levelization supported

• 8 bit pre-fetch