4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant)

FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All a

文件：472.76 Kbytes 页数：33 Pages

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4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant)

FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All a

文件：472.76 Kbytes 页数：33 Pages

HYNIX

海力士

4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant)

FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All a

文件：472.76 Kbytes 页数：33 Pages

HYNIX

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4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant)

FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All a

文件：472.76 Kbytes 页数：33 Pages

HYNIX

海力士

4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant)

FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All a

文件：472.76 Kbytes 页数：33 Pages

HYNIX

海力士

4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant)

FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All a

文件：472.76 Kbytes 页数：33 Pages

HYNIX

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DDR3 SDRAM

The H5TC4G63CFR-xxA a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment wi • VDD=VDDQ=1.35V + 0.100 / - 0.067V\n• Fully differential clock inputs (CK, CK) operation\n• Differential Data Strobe (DQS, DQS)\n• On chip DLL align DQ, DQS and DQS transition with CK transition\n• DM masks write data-in at the both rising and falling edges of the data strobe\n• All addresses and c;

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