H5DU2562GFR中文资料256Mb DDR SDRAM数据手册SK hynix规格书

描述 Description

DESCRIPTION
The H5DU2562GFR is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.FEATURES
•VDD, VDDQ= 2.5V +/- 0.2V
• All inputs and outputs are compatible with SSTL_2 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
  Data inputs on DQS centers when write (centered DQ)
• On chip DLL align DQ and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 2/2.5 (DDR200, 266, 333), 3 (DDR400) and 4 (DDR500) supported
• Programmable burst length 2/4/8 with both sequential and interleave mode
• Internal four bank operations with single pulsed/RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles/64ms
•60 Ball FBGA Package Type
• This product is in compliance with the directive pertaining of RoHS.

特性 Features

•VDD, VDDQ= 2.5V +/- 0.2V
• All inputs and outputs are compatible with SSTL_2 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
  Data inputs on DQS centers when write (centered DQ)
• On chip DLL align DQ and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 2/2.5 (DDR200, 266, 333), 3 (DDR400) and 4 (DDR500) supported
• Programmable burst length 2/4/8 with both sequential and interleave mode
• Internal four bank operations with single pulsed/RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles/64ms
•60 Ball FBGA Package Type
• This product is in compliance with the directive pertaining of RoHS.