HP5 CYCL-FLEX짰 Reset Timer

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3A Bus Termination Regulator

[HiPAC] General Description The HPL5331 linear regulator is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. The HPL5331 integrates two power transistors to source or sink current up to 3A. It also incorporate current-limit, thermal shutdown a

文件：260.88 Kbytes 页数：20 Pages

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3A Bus Termination Regulator

[HiPAC] General Description The HPL5331 linear regulator is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. The HPL5331 integrates two power transistors to source or sink current up to 3A. It also incorporate current-limit, thermal shutdown a

文件：260.88 Kbytes 页数：20 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

3A Bus Termination Regulator

[HiPAC] General Description The HPL5331 linear regulator is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. The HPL5331 integrates two power transistors to source or sink current up to 3A. It also incorporate current-limit, thermal shutdown a

文件：260.88 Kbytes 页数：20 Pages

ETCList of Unclassifed Manufacturers

未分类制造商