GTL2006PW

13-bit GTL-/GTL/GTL to LVTTL translator

DESCRIPTION TheGTL2006isa13-bittranslatortointerfacebetweenthe3.3VLVTTLchipsetI/OandtheXeonprocessorGTL–/GTL/GTL+I/O.TheGTL2006isdesignedforplatformhealthmanagementindualprocessorapplications. FEATURES •OperatesasaGTL–/GTL/GTL+toLVTTLsamplingreceiveror

GTL2006PW

13位GTL-/GTL/GTL+至LVTTL变换器; • Operates as a GTL�/GTL/GTL+ to LVTTL sampling receiver or LVTTL to GTL�/GTL/GTL+ driver\n• 3.0 V to 3.6 V operation\n• LVTTL I/O not 5 V tolerant\n• Series termination on the LVTTL outputs of 30 Ω\n• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101\n• Latch-up testing is done to JESDEC Standard JESD78 which exceeds 500 mA\n• Package offered: TSSOP28\n;

The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the XeonTMprocessor GTL�/GTL/GTL+ I/O. The GTL2006 is designed for platform health management in dual processor applications.\n

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