GS840E18AB-100中文资料GSI数据手册PDF规格书

Functional Description

Applications

The GS840E18/32/36A is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2- bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS84018/32/36A is available in a JEDEC standard 100-lead TQFP or 119-Bump BGA package.

特性 Features

• FT pin for user-configurable flow through or pipelined operation

• Dual Cycle Deselect (DCD) operation

• 3.3 V +10/–5 core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or 119-Bump BGA package

• Pb-Free 100-lead TQFP package available