GS84018AB-100数据手册GSI中文资料规格书

特性 Features

• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.Applications
  The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS84018/32/36 is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA package.