GS8324Z72C-133I中文资料GSI数据手册PDF规格书

特性 Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• FT pin for user-configurable flow through or pipeline operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10/–5 core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 209-bump BGA package

Applications

The GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die

synchronous SRAM module with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device now

finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.