GS820V32T中文资料GSI数据手册PDF规格书

Functional Description

The GS820V32 is a 64Kx32 high performance synchronous SRAM with 2 bit burst counter. It is designed to provide L2 Cache for PentiumTM and other high performance CPU. Addresses (A0-15), data IOs (DQ1-32), chip enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC, ADV) and write control inputs (BW1, BW2, BW3, BW4, BWE, GW) are synchronous and are controlled by a positive edge triggered clock (CLK).

特性 Features

• Single 3.3V +5/-5 power supply

• Separate VDDQ to allow 2.375V to 3.465V output supply level

• High frequency operation: 117MHz

• Fast access time: 4.5ns Clock to Q

• Low power: 0.5mA ISB and IDD static

• FT mode pin for either flow-thru or pipeline operation

• LBO mode pin for linear or interleave (PentiumTM and X86) burst mode

• Byte write (BWE) and global write (GW) operation

• 3 chip enable signals for easy depth expansion

• 2 cycles enable (pipeline mode) and 1 cycle disable to allow multiple bank without data buss contention

• Compatible to both 3.3V and 2.5V interface level

• Standard Industrial Temperature Option: -40 to +85C

• JEDEC standard 100 lead package:

Q: QFP

T: TQFP