64K x 32 2Mb Synchronous Burst SRAM

Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10/–5 core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating m

文件：577.31 Kbytes 页数：22 Pages

GSI

64K x 32 2Mb Synchronous Burst SRAM

Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10/–5 core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating m

文件：577.31 Kbytes 页数：22 Pages

GSI

64K x 32 2Mb Synchronous Burst SRAM

Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10/–5 core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating m

文件：577.31 Kbytes 页数：22 Pages

GSI

64K x 32 2Mb Synchronous Burst SRAM

Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10/–5 core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating m

文件：577.31 Kbytes 页数：22 Pages

GSI

64K x 32 2M Synchronous Burst SRAM

Functional Description Applications The GS82032A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM

文件：677.23 Kbytes 页数：23 Pages

GSI

64K x 32 2M Synchronous Burst SRAM

Functional Description Applications The GS82032A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM

文件：677.23 Kbytes 页数：23 Pages

GSI

64K x 32 2Mb Synchronous Burst SRAM

Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10/–5 core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating m

文件：577.31 Kbytes 页数：22 Pages

GSI

64K x 32 2Mb Synchronous Burst SRAM

Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10/–5 core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating m

文件：577.31 Kbytes 页数：22 Pages

GSI

64K x 32 2Mb Synchronous Burst SRAM

Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10/–5 core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating m

文件：577.31 Kbytes 页数：22 Pages

GSI

64K x 32 2Mb Synchronous Burst SRAM

Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10/–5 core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating m

文件：577.31 Kbytes 页数：22 Pages

GSI