1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs

Functional Description Applications The GS816218/36BB is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronou

文件：1.46281 Mbytes 页数：37 Pages

GSI

1M x 18, 512K x 36 18Mb S/DCD Sync Burst SRAMs

Functional Description Applications The GS816218/36BB is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronou

文件：618.33 Kbytes 页数：31 Pages

GSI

1M x 18, 512K x 36 18Mb S/DCD Sync Burst SRAMs

Functional Description Applications The GS816218/36BB is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronou

文件：618.33 Kbytes 页数：31 Pages

GSI

1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs

Functional Description Applications The GS816218/36BB is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronou

文件：1.46281 Mbytes 页数：37 Pages

GSI

1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs

Functional Description Applications The GS8162xxBB-xxxV is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchron

文件：1.20405 Mbytes 页数：31 Pages

GSI

1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs

Functional Description Applications The GS8162xxBB-xxxV is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchron

文件：1.20405 Mbytes 页数：31 Pages

GSI