GPL81201A中文资料Low Power 84-Dot LCD Controller with 8KB ROM数据手册Generalplus规格书

描述 Description

The GPL81201A, a chip designed for LCD display embedded with 128 bytes SRAM and 8K bytes ROM, features four timers and up to 15 software selectable general I/Os. It operates over a wide voltage range of 1.8 - 3.6V@ 4/8MHz and has a sleep mode for power saving mode, which retains the contents of RAM, but stops the oscillator and causes all other chip functions to be inoperative. Sleep mode can be released by using external wakeup sources or time base wakeup source. This device is applicable for many applications such as low power watch and other LCD-based products.

特性 Features

• Built-in 8-bit processor
• 128-byte SRAM
• 8K-byte ROM
• 128 bit DPRAM
• Built-in 4M/8MHz Crystal or IOSC for system operation

• internal oscillator with ±5% precision .

• Built-in 32KHz IOSC or 32768Hz Crystal oscillator circuit for timebase.
• Operating voltage: 

• 4.0MHz@1.8V~3.6V or 8.0MHz@1.8V~3.6V

• Built-in Standby mode (Clock Stop mode) & Halt mode(with LCD and 32K timer on) for power saving

• Low standby current, ISTBY < 1u @3.6V, 25??/li>
• Low halt mode current, Ihalt < 8u @3.6V, 25??/li>

• Up to 15 bi-directional tri-state I/O ports

• Port A[7:0]: with programmable pull high / pull low / floating, share pads with SEGMENT[23:16]
• Port C[1:0]: with programmable pull high / pull low / floating, share pads with SEGMENT[25:24].
• Port D[7],D[1:0]: with programmable pull high / pull low / floating.
• Port D[3:2]: with programmable pull high / pull low / floating, share pads with X32O, X32I.

• LCD configurations: 4 coms x 21 segs (MAX)

• Frame rate is 85Hz.
• LCD 1/3 bias; 1/3, 1/4 duty; VLCD = VDD

• Four timers

• Basic timer provides Fosc/4194304 watch dog source;
• Timer0 is a general purpose 8-bit timer with input clock selectable;
• Timer1 is a general purpose 12-bit timer with input clock selectable
• 32K timer is a time base wakeup source with frequency selectable

• 8 interrupt sources

• TM0O, TM1O, CPUDiv1K, CPUDiv4K, CPUDiv32K, CPUDiv2M, TBHF, TBLF.

• Wakeup source

• Key (Port C/D) change wakeup
• 32K time base wakeup(TBHF/TBLF)

• LVD (Low voltage detect)

• Sense VDD voltage@ 2.1V / 2.4V (register option)
Note1: TBHF: 128Hz, 256Hz, 512Hz or 1KHzNote2: TBLF: 2Hz, 4Hz, 8Hz or 16Hz