GPCM300A数据手册Generalplus中文资料规格书

描述 Description

The industrial microcontroller of GPCM3 series equips ARM® Cortex®-M0 processor core and 32-channel sound process unit (SPU), operating at a frequency of up to 122.88MHz. The GPCM3 series is applicable for the applications of digital sound processing and voice recognition, etc.

特性 Features

• CPU
• CPU Core
• ARM® Cortex®-M0 32-bit CPU (122.88MHz max) with Code Fetch Accelerator
• Nested Vectored Interrupt Controller (NVIC) with 32 interrupt sources
• 24-bit SysTick timer
• Single cycle 32-bit multiplier instruction


• 32-channel SPU
• Memory
• 32K-byte SRAM and 8K-byte Cache RAM
• running SPI external code and data in auto mode

• Clock Management
• Internal288MHz oscillator and XTAL 12M crystal
• Phase Lock Loop with configurable output frequency: 122.88M Hz (max)
• Internal 32768Hz oscillator and XTAL 32768Hz crystal

• Power Management
• In Shutdown mode: Core power and all clocks are stopped
• In Deep Sleep mode: CPU clocks off, system entering deep sleep mode ,and all clock off
• In Halt mode: CPU clocks off, system entering deep sleep mode, and only 32768Hz clock on.
• In Sleep mode: Only CPU Clock off
• Regulator with configurable output SPI Voltage and Codec voltage
• Battery Voltage Detection

• Reset Management
• Power On Reset
• Low Voltage Reset
• Watchdog Timeout Reset
• PAD(H/W Key)Reset
• S/W Reset

• Analog peripherals
• 16-bit Audio PWM
• 16-bit DAC x 2
• 16-bit Sigma Delta Codec ADC(MIC ADC)
• 12-bit SAR ADC and 8 x line-in PADs
• CTS(Capacitor sensing touch) supporting 32 x Touch IO PADs

• I/O Ports
• 43 (include SPIFC) multifunction and bi-direction I/Os
• I/O ports with pull-up resistor, pull-down resistor, output high, output low or floating input, and configurable source/sink current depending on programmer’s settings on the corresponding registers
• IOA can be set External Key for CPU wakeup.

• System Control
• Five-channel DMA controller
• System Management Unit (SMU) for system configuration and control
• HW 16x16 MAC for accumulator
• HW 32x16 MAC function
• HW 32/32 Divider function
• Two quadrature decoders

• Timer
• Three general-purpose 16-bit timers/counters
• Two 16-bit touch sensing timers for CTS
• Two 16-bit CCP timers(Capture/Compare/PWM) Units and 16 PWMIOs

All of them can be used as general- purpose timers.
• Communication peripherals
• One I2C hardware
• One I2S TX and I2S RX.
• One SPIFC (SPI controller for FLASH device access) and two SPI serial interface I/Os
• Two UART hardware
• One IR TX hardware

• SAR ADC Controller
• 12-bit resolution SAR ADC and 10-channel selection (8*LINE-IN, VDD12 and VDD_IO/4)
• Supporting single, regular and regular scan conversion mode
• Data alignment with left-aligned and right-aligned
• External trigger option for injected conversion
• Analog detection watchdog
• DMA request generation during channel conversion

• PDM
• Pulse-density modulation MES MIC

• SDM ADC Controller(MIC ADC)
• 16-bit resolution Sigma-Delta Modulation ADC (SDM ADC) with Digital Audio gain control(DAGC)
• DMA request generation during ADC conversion

• DAC Controller
• Supporting two input channel and 4x Up-Sampling
• Supporting scale/truncation mode when data saturation
• DMA request generation during DAC data done
• Output to 16-bit Audio PWM or 16-bit DAC
• Audio PWM support digital gain control and auto mute control

• USB Device Controller
• Supports USB1.1 / USB2.0(full speed) compliant device with built-in transceiver

• Debug System
• ARM serial wire debug (SWD)
• Supporting up to three hardware breakpoints

• Operation Temperature
• -40°C to 85°C

• Package
• LQFP64