Overview

GMS30C2116/32 RISC/DSP

The GMS30C2116 and GMS30C2132 RISC/DSP present a new class of microprocessors: The combination of a high-performance RISC microprocessor with an additional powerful DSP instruction set and on-chip micro-controller functions. The high throughput is not achieved by raw clock speed, it is due to a sophisticated novel architecture, combining the advantages of RISC and DSP technology.

The speed is obtained by an optimized combination of the following features:

• The most recent stack frames are kept in a register stack, thereby reducing data memory accesses to a minimum by keeping almost all local data in registers.

• Pipelined memory access allows overlapping of memory accesses with execution.

• 4KByte on-chip memory.

• On-chip instruction cache omits instruction fetch in inner loops and provides pre-fetch.

• Variable-length instructions of 16, 32 or 48 bits provide a large, powerful instruction set, thereby reducing the number of instructions to be executed.

• Primarily used 16-bit instructions halve the memory bandwidth required for instruction fetch in comparison to conventional RISC architectures with fixed-length 32-bit instructions, yielding also even better code economy than conventional CISC architectures.

• Regular instruction set allows hardwiring of control logic at low component count.

• Most instructions execute in one cycle.

• Pipelined DSP instructions.

• Parallel execution of ALU and DSP instructions.

• Single-cycle half word multiply-accumulate operation.

• Fast Call and Return by parameter passing via registers.

• An instruction pipeline depth of only two stages - decode/execute - provides branching without insertion of wait cycles in combination with Delayed Branch instructions.

• Range and pointer checks are performed without speed penalty, thus, these checks need no longer be turned off, thereby providing higher runtime reliability.

• Separate address and data buses provide a throughput of one 32-bit word each cycle.