MUN5316DW

DUALBIASRESISTORTRANSISTORNPN&PNPWITHMONOLITHICBIASRESISTORNETWORK

DESCRIPTION TheBRT(BiasResistorTransistor)containsasingle transistorwithamonolithicbiasnetworkconsisting oftworesistors;aseriesbaseresistoranda baseemitterresistor.Thesedigitaltransistorsare designedtoreplaceasingledeviceanditsexternal resistorbiasnetwor

MUN5316DW

DualBiasResistorTransistors

MUN5316DW

DualBiasResistorTransistorNPNPNPSilicon

DualBiasResistorTransistor NPN+PNPSilicon P/bLead(Pb)-Free

NCP5316

Four/Five/Six?뭁haseBuckCPUController

NCP5316

Four/Five/Six-PhaseBuckCPUController

PM5316

QuadChannel155Mbit/sSONET/SDHFramerandAligner

FEATURES •MonolithicfourchannelSONET/SDHPayloadExtractor/AlignerforuseinSTS-3(STM-1/AU-3)orSTS-3c(STM-1/AU-4)interfaceapplications,operatingatserialinterfacespeedsof155.52Mbit/s. •Providesintegratedclockrecoveryandclocksynthesistoallowdirectinterfacetooptical

PM5316

SONET/SDHPayloadExtractor/Aligner(4x155Mbit/s)

PM5316

QuadChannel155Mbit/sSONET/SDHFramerandAligner

Features General •MonolithicfourchannelSONET/SDHPayloadExtractor/AlignerforuseinSTS-3(STM-1/AU-3)orSTS-3c(STM-1/AU-4)interfaceapplications,operatingatserialinterfacespeedsof155.52Mbit/s. •Providesintegratedclockrecoveryandclocksynthesisfordirectinterfacingwith

PM5316-BI

SONET/SDHPayloadExtractor/Aligner(4x155Mbit/s)

SI5316

PRECISIONCLOCKJITTERATTENUATOR

Features Fixedfrequencyjitterattenuator withselectableclockrangesat 19,38,77,155,311,and 622MHz(710MHzmax) SupportforSONET,10GbE, 10GFC,andcorrespondingFEC rates Ultra-lowjitterclockoutputwith jittergenerationaslowas 0.3psRMS(50kHz–80MHz) Integr