GAL20V8C-10LP中文资料下载批发采购莱迪思-114ic电子网

型号	下载订购	功能描述	制造商上传企业	LOGO
GAL20V8C-10LP	文件：308.03 Kbytes Page：23 Pages	High Performance E2CMOS PLD Generic Array Logic Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( 文件：308.03 Kbytes 页数：23 Pages	Lattice 莱迪思	Lattice
GAL20V8C-10LJ	文件：582.78 Kbytes Page：25 Pages	High Performance E2CMOS PLD Generic Array Logic? 文件：582.78 Kbytes 页数：25 Pages	Lattice 莱迪思	Lattice
GAL20V8C-10LJI	文件：308.03 Kbytes Page：23 Pages	High Performance E2CMOS PLD Generic Array Logic Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( 文件：308.03 Kbytes 页数：23 Pages	Lattice 莱迪思	Lattice
GAL20V8C-10LJI	文件：582.78 Kbytes Page：25 Pages	High Performance E2CMOS PLD Generic Array Logic? 文件：582.78 Kbytes 页数：25 Pages	Lattice 莱迪思	Lattice

更多GAL20V8C-10LP供应商更新时间2025-10-4 14:01:00