Description

The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.

The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20V8 are the PAL architectures listed in the table of the macrocell description section. GAL20V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

— 5 ns Maximum Propagation Delay

— Fmax = 166 MHz

— 4 ns Maximum from Clock Input to Data Output

— UltraMOS® Advanced CMOS Technology

• 50 to 75 REDUCTION IN POWER FROM BIPOLAR

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

• ACTIVE PULL-UPS ON ALL PINS

• E2 CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100 Tested/100 Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 24-pin PAL® Devices with Full Function/Fuse Map/Parametric Compatibility

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100 Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

GAL20V8B-25QJ属于集成电路（IC） > CPLD（复杂可编程逻辑器件）。莱迪思半导体制造生产的GAL20V8B-25QJCPLD（复杂可编程逻辑器件）CPLD 是用于执行逻辑运算和信息处理的用户可配置集成电路产品；与 PLD 或 PAL 器件相比，这些器件具有更高级别的功能（即更多的逻辑门），但低于 FPGA。CPLD 通常包含非易失性配置存储器，支持直接在器件上存储和保留用户所需的配置，并在器件断电时仍可保留这些信息。