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G522-0267-00中文资料PDF规格书
G522-0267-00规格书详情
Features
This section summarizes features of the 603e’s implementation of the PowerPC architecture. Major features
of the 603e are as follows:
• High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
• Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
integer add/compare instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
• High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— 16-Kbyte instruction cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
• Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
• Integrated power management
— Low-power 2.5/3.3-volt design
— Internal processor/bus clock multiplier that provides 2/1, 2.5/1, 3/1, 3.5/1, 4/1, 4.5/1, 5/1,
5.5/1, and 6/1 ratios
— Three power saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• In-system testability and debugging features through JTAG boundary-scan capability
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
GMT |
20+ |
SOT153 |
32970 |
原装优势主营型号-可开原型号增税票 |
询价 | ||
GMT |
2016+ |
SOT153 |
3000 |
只做原装,假一罚十,公司可开17%增值税发票! |
询价 | ||
GMT |
23+ |
SOT23-5 |
20000 |
原厂原装正品现货 |
询价 | ||
GMT/致新 |
23+ |
12000 |
原装现货 |
询价 | |||
Wcon(维峰电子) |
21+ |
- |
4750 |
中国航天工业部战略合作伙伴行业领导者 |
询价 | ||
GMT |
2023+ |
SOT23-5 |
80000 |
一级代理/分销渠道价格优势 十年芯程一路只做原装正品 |
询价 | ||
GMT |
21+ |
SOT23-5 |
18689 |
原装现货假一赔十 |
询价 | ||
GMT/致新 |
21+ |
SOT153 |
20000 |
全新原装 公司现货 价优 |
询价 | ||
GMT |
2018+ |
SOT23 |
20000 |
一级代理原装现货假一罚十 |
询价 | ||
GMT(致新) |
21+ |
QFN24 |
3800 |
询价 |