FW322中文资料1394A PCI PHY/Link Open Host Controller Interface数据手册Broadcom规格书

特性 Features

■ 1394a-2000 OHCI link and PHY core function in sin gle device:
   — Enables smaller, simpler, more efficient mother board and add-in card designs by replacing two components with one
   — Enables lower system costs
   — Leverages proven 1394a-2000 PHY core design
   — Demonstrated compatibility with current Microsoft Windows* drivers and common applications
   — Demonstrated interoperability with existing, as well as older, 1394 consumer electronics and periph erals products
   — Feature-rich implementation for high performance in common applications
   — Supports low-power system designs (CMOS implementation, power management features)
   — Provides LPS, LKON, and CNA outputs to support legacy power management implementations
■ OHCI:
   — Complies with 1394 OHCI specification revision 1.0
   — Supports the following 1394 OHCI revision 1.1 features:
      ❑ Isochronous receive dual-buffer mode.
      ❑ Enhanced isochronous transmit skip/overflow support.
      ❑ ack_data_error improvememnts for asynchro nous and physical requests.
      ❑ Enhanced CSR control register implementation.
      ❑ Autonomous configuration ROM updates.
      ❑ Enhanced power management support, including ack_tardy event.
      ❑ Enhanced SelfID protocol, including selfIDComplete2 event.
   — Compatible with Microsoft OHCI, DV, and SBP-2 driver stack in W98, W98SE, W2000, and MacOS† operating system
   — 4 Kbyte isochronous transmit FIFO
   — 2 Kbyte asynchronous transmit FIFO
   — 4 Kbyte isochronous receive FIFO
   — 2 Kbyte asychronous receive FIFO
   — Dedicated asynchronous and isochronous descriptor-based DMA engines
   — Eight isochronous transmit contexts
   — Eight isochronous receive contexts
   — Prefetches isochronous transmit data
   — Supports posted write transactions
  
■ 1394a-2000 PHY core:
   — Compliant with IEEE‡ 1394a-2000, Standard for a High Performance Serial Bus (Supplement)
   — Provides two fully compliant cable ports each supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic
   — Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders
   — While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port
   — Does not require external filter capacitor for PLL
   — Supports PHY core-link interface initialization and reset
   — Supports link-on as a part of the internal PHY core-link interface
   — 25 MHz crystal oscillator and internal PLL provide transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s, and internal link-layer controller clock at 50 MHz
   — Interoperable across 1394 cable with 1394 physical layers (PHY core) using 5 V supplies
   — Node power-class information signaling for system power management
   — Supports ack-accelerated arbitration and fly-by concatenation
   — Supports arbitrated short bus reset to improve utilization of the bus
   — Fully supports suspend/resume
   — Supports connection debounce
   — Supports multispeed packet concatenation
   — Supports PHY pinging and remote PHY access packets
   — Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V
   — Separate cable bias and driver termination voltage supply for each port
■ Link:
   — Cycle master and isochronous resource manager capable
   — Supports 1394a-2000 acceleration features