FR30数据手册Fujitsu中文资料规格书

描述 Description

■ DESCRIPTION
This model, designed on the basis of 32-bit RISC CPU (FR30 series), is a standard single-chip micro controller with built-in I/O resources and bus control functions. The functions are suitable for built-in control that requires high-speed CPU processing.
MB91F127 includes 256 Kbytes built-in flash memory and 14 Kbytes built-in RAM. MB91F128 includes 510 Kbytes built-in flash memory and 14 Kbytes built-in RAM.
The specifications of the devices are best suited for applications requiring high-level CPU processing capabilities, such as navigation system, high-performance FAX, and printer controller.■ FEATURES
FR-CPU
• 32-bit RISC (FR30), load/store architecture, 5-step pipeline
• Operating frequency : Internal 25 MHz
• General register : 32bit x 16 registers
• 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle
• Instructions of memory-to-memory transfer, bit processing, and barrel shift : Instructions suitable for built-incontrol
• Function entry/exit instructions, multi load/store instruction for register data : High-level language compatible instructions
• Register interlock functions : Simple description of assembler language
• Branch instructions with delay slot : Reduced overhead on branching process
• Built-in multiplier/ Supporting at instruction level
  Signed 32-bit multiplying : 5 cycles
  Signed 16-bit multiplying : 3 cycles
• Interrupt (saving PC and PS) : 6 cycles, 16 priority levelsBus interface
• Maximum of 25 MHz internal operation rate
• 25-bit address bus (32 MB space)
• 16-bit address output, 8/16-bit data input/output
• Basic bus cycle : 2-clock cycle
• Chip selection outputs specifiable in a minimum of 64 Kbytes steps : 6 outputs
• Automatic wait cycle : Specifiable flexibly from 0 cycle to 7 cycles for each area
• Supporting time-division input/output interface for address/data (for area 1 only)
• Unassigned data/address terminals are available as input/output ports
• Supporting little endian mode (selecting one area from area 1 to area 5)DMAC (DMA controller)
• 8 channels
• Transfer factor : Interrupt request of built-in resources
• Transfer sequence : Step transfer/Block transfer/Burst transfer/Consecutive transfer
• Transfer data length : Selectable among 8 bits, 16 bits, and 32 bits
• Pausing is allowed by interrupt requestUART
• 3 channels
• Full-duplex double buffer
• Data length : 7 to 9 bits (no parity), 6 to 8 bits (with parity)
• Asynchronous (start-stop synchronization) or CLK synchronous communication is selectable
• Multi processor mode
• Built-in 16-bit timer (U-Timer) used as a baud-rate generator : Generates an arbitrary baud rate
• External clock is available as a transfer clock
• Error detection : parity, frame, and overrunA/D converter (sequential transducer)
• 8/10-bit resolution, 8 channels
• Sequential comparison and transducer : At 25 MHz, 5.2 µs
• Built-in sample and hold circuit
• Conversion mode : Selectable among single conversion, scan conversion, and repeat conversion
• Activation : Selectable among software, external trigger, and built-in timerReload timer
• 16-bit timer : 3 channels
• Internal clock : 2-clock cycle resolution, selectable among 2/8/32 dividing and external clock

特性 Features

FR-CPU
• 32-bit RISC (FR30), load/store architecture, 5-step pipeline
• Operating frequency : Internal 25 MHz
• General register : 32bit x 16 registers
• 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle
• Instructions of memory-to-memory transfer, bit processing, and barrel shift : Instructions suitable for built-incontrol
• Function entry/exit instructions, multi load/store instruction for register data : High-level language compatible instructions
• Register interlock functions : Simple description of assembler language
• Branch instructions with delay slot : Reduced overhead on branching process
• Built-in multiplier/ Supporting at instruction level
  Signed 32-bit multiplying : 5 cycles
  Signed 16-bit multiplying : 3 cycles
• Interrupt (saving PC and PS) : 6 cycles, 16 priority levelsBus interface
• Maximum of 25 MHz internal operation rate
• 25-bit address bus (32 MB space)
• 16-bit address output, 8/16-bit data input/output
• Basic bus cycle : 2-clock cycle
• Chip selection outputs specifiable in a minimum of 64 Kbytes steps : 6 outputs
• Automatic wait cycle : Specifiable flexibly from 0 cycle to 7 cycles for each area
• Supporting time-division input/output interface for address/data (for area 1 only)
• Unassigned data/address terminals are available as input/output ports
• Supporting little endian mode (selecting one area from area 1 to area 5)DMAC (DMA controller)
• 8 channels
• Transfer factor : Interrupt request of built-in resources
• Transfer sequence : Step transfer/Block transfer/Burst transfer/Consecutive transfer
• Transfer data length : Selectable among 8 bits, 16 bits, and 32 bits
• Pausing is allowed by interrupt requestUART
• 3 channels
• Full-duplex double buffer
• Data length : 7 to 9 bits (no parity), 6 to 8 bits (with parity)
• Asynchronous (start-stop synchronization) or CLK synchronous communication is selectable
• Multi processor mode
• Built-in 16-bit timer (U-Timer) used as a baud-rate generator : Generates an arbitrary baud rate
• External clock is available as a transfer clock
• Error detection : parity, frame, and overrunA/D converter (sequential transducer)
• 8/10-bit resolution, 8 channels
• Sequential comparison and transducer : At 25 MHz, 5.2 µs
• Built-in sample and hold circuit
• Conversion mode : Selectable among single conversion, scan conversion, and repeat conversion
• Activation : Selectable among software, external trigger, and built-in timerReload timer
• 16-bit timer : 3 channels
• Internal clock : 2-clock cycle resolution, selectable among 2/8/32 dividing and external clock