ESP32-C6中文资料乐鑫科技数据手册PDF规格书

Features

Wi-Fi

• 1T1R in 2.4 GHz band

• Operating frequency: 2412 ~ 2484 MHz

• IEEE 802.11ax-compliant

– 20 MHz-only non-AP mode

– MCS0 ~MCS9

– Uplink and downlink OFDMA, especially

suitable for simultaneous connections in

high-density environments

– Downlink MU-MIMO (multi-user, multiple

input, multiple output) to increase network

capacity

– Beamformee that improves signal quality

– Channel quality indication (CQI)

– DCM (dual carrier modulation) to improve

link robustness

– Spatial reuse to maximize parallel

transmissions

– Target wake time (TWT) that optimizes

power saving mechanisms

• Fully compatible with IEEE 802.11b/g/n protocol

– 20 MHz and 40 MHz bandwidth

– Data rate up to 150 Mbps

– Wi-Fi Multimedia (WMM)

– TX/RX A-MPDU, TX/RX A-MSDU

– Immediate Block ACK

– Fragmentation and defragmentation

– Transmit opportunity (TXOP)

– Automatic Beacon monitoring (hardware

TSF)

– Four virtual Wi-Fi interfaces

– Simultaneous support for Infrastructure

BSS in Station mode, SoftAP mode, Station

+ SoftAP mode, and promiscuous mode.

Note that when ESP32-C6 scans in Station

mode, the SoftAP channel will change

along with the Station channel

– Antenna diversity

– 802.11mc FTM

Bluetooth®

• Bluetooth LE: Bluetooth 5.3 certified

• Bluetooth mesh

• High power mode (20 dBm)

• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps

• Advertising extensions

• Multiple advertisement sets

• Channel selection algorithm #2

• LE power control

• Internal co-existence mechanism between Wi-Fi

and Bluetooth to share the same antenna

IEEE 802.15.4

• Compliant with IEEE 802.15.4-2015 protocol

• OQPSK PHY in 2.4 GHz band

• Data rate: 250 Kbps

• Thread 1.3

• Zigbee 3.0

CPU and Memory

• HP RISC-V processor:

– Clock speed: up to 160 MHz

– Four stage pipeline

– CoreMark® score: 496.66 CoreMark; 3.10

CoreMark/MHz (160 MHz)

• LP RISC-V processor:

– Clock speed: up to 20 MHz

– Two stage pipeline

• L1 cache: 32 KB

• ROM: 320 KB

• HP SRAM: 512 KB

• LP SRAM: 16 KB

• Supported SPI protocols: SPI, Dual SPI, Quad

SPI, QPI interfaces that allow connection to flash

and other SPI devices off the chip’s package

• Flash controller with cache is supported

• Flash in-Circuit Programming (ICP) is supported