EQ50F100数据手册集成电路（IC）的专用规格书PDF

描述 Description

The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for up to 30\" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps Ethernet Systems.

The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm 6-pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.



The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for up to 30\" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps Ethernet Systems.

The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm 6-pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.

特性 Features

• Recovers 6.25 Gbps signals after 30\" of FR4
• Single 1.8V power supply
• Low power consumption: 85mW
• Equalize up to 20dB loss at 2.5 GHz
• 35 ps residual deterministic jitter at 5 Gbps
• On-chip CML terminations
• Small 3 mm x 3 mm 6-pin leadless LLP package