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EPM7192EGC160-15中文资料PDF规格书
EPM7192EGC160-15规格书详情
General Description
The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
Features...
■ High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX® architecture
■ 5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see Tables 1 and 2)
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
■ PCI-compliant devices available
■ Open-drain output option in MAX 7000S devices
■ Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
■ Programmable power-saving mode for a reduction of over 50 in
each macrocell
■ Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
■ Programmable security bit for protection of proprietary designs
■ 3.3-V or 5.0-V operation
– MultiVoltTM I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
■ Enhanced features available in MAX 7000E and MAX 7000S devices
– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
– Programmable output slew-rate control
■ Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
■ Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, and VeriBest
■ Programming support
– Altera’s Master Programming Unit (MPU) and programming
hardware from third-party manufacturers program all
MAX 7000 devices
– The BitBlasterTM serial download cable, ByteBlasterMVTM
parallel port download cable, and MasterBlasterTM
serial/universal serial bus (USB) download cable program MAX
7000S devices
产品属性
- 型号:
EPM7192EGC160-15
- 功能描述:
CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 192 Macro 124 IOs
- RoHS:
否
- 制造商:
Lattice
- 存储类型:
EEPROM
- 大电池数量:
128
- 最大工作频率:
333 MHz
- 延迟时间:
2.7 ns
- 可编程输入/输出端数量:
64
- 工作电源电压:
3.3 V
- 最大工作温度:
+ 90 C
- 最小工作温度:
0 C
- 封装/箱体:
TQFP-100
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
ALTERA |
23+ |
PGA |
18689 |
询价 | |||
ALTERA |
2020+ |
QFP |
35000 |
新到原装货,专营系列:查询请Q我 |
询价 | ||
ALTERA |
23+ |
PGA |
15000 |
全新原装现货假一赔十 |
询价 | ||
ALTERA/阿尔特拉 |
23+ |
BGA160 |
6888998 |
一站式BOM配单 |
询价 | ||
ALTERA |
1420+ |
PGA |
6700 |
公司主营ALTERA系列,全新原装,正品供应 |
询价 | ||
ALTERA |
22+ |
BGA |
500 |
保证有货!质优价美!欢迎查询!! |
询价 | ||
Altera |
10 |
公司优势库存 热卖中!! |
询价 | ||||
ALTERA |
PGA-160 |
13500 |
16余年资质 绝对原盒原盘 更多数量 |
询价 | |||
ALTERA/阿尔特拉 |
23+ |
PGA |
50000 |
全新原装正品现货,支持订货 |
询价 | ||
ALTERA/阿尔特拉 |
23+ |
TO-59 |
8510 |
原装正品代理渠道价格优势 |
询价 |