Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.4977 Mbytes 页数：66 Pages

Altera

阿尔特

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.4977 Mbytes 页数：66 Pages

Altera

阿尔特

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.4977 Mbytes 页数：66 Pages

Altera

阿尔特

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.4977 Mbytes 页数：66 Pages

Altera

阿尔特

High-performance, EEPROM-based programmable logic devices PLDs) based on second-generation MAX architecture

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.48645 Mbytes 页数：66 Pages

Altera

阿尔特

Programmable Logic Device Family

General Description\nThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter

Intel

英特尔

Package：100-BQFP；包装：托盘 类别：集成电路（IC） CPLD（复杂可编程逻辑器件） 描述：IC CPLD 128MC 10NS 100QFP

Intel

英特尔

Package：100-BQFP；包装：托盘 类别：集成电路（IC） CPLD（复杂可编程逻辑器件） 描述：IC CPLD 128MC 10NS 100QFP

Intel

英特尔

Package：100-BQFP；包装：托盘 类别：集成电路（IC） CPLD（复杂可编程逻辑器件） 描述：IC CPLD 128MC 15NS 100QFP

Intel

英特尔