Programmable logic , 64 macrocells, 4 logic array blocks, 36 I/O pins, 10ns

Description\nThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP,pin-to-pin delays as fast as 5 ns, and counter speeds of \n■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX®architecture\n■ 5.0-V in-system programmability(ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices\n– ISP circuitry compatible with IEEE;

Intel

英特尔

BGA

ALTERA

阿尔特

上传：深圳市胜彬电子有限公司

QFP

ALTERA

阿尔特

上传：深圳市胜彬电子有限公司

ALTERA

阿尔特

上传：深圳市毅创辉电子科技有限公司

QFP100

alterA

上传：深圳市拓亿芯电子有限公司