EPM7064STC44-10N中文资料EPM7064STC44-10N - 芯片, 可编程逻辑器件 MAX ISP PLD数据手册Intel规格书

描述 Description

The EPM7064STC44-10N is a high-density, high-performance Programmable Logic Device (PLD) based on second-generation MAX® architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5000 usable gates, ISP, pin-to-pin delays as fast as 5ns and counter speeds of up to 175.4MHz. Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys and VeriBest.

特性 Features

·Built-in JTAG boundary-scan test
·PCI-compliant devices available
·5ns pin-to-pin logic delays with up to 175.4MHz counter frequencies
·Open-drain output option
·Programmable macrocell flip-flops with individual clear, preset, clock and clock enable controls
·Programmable power-saving mode for a reduction of over 50% in each macrocell
·Six pin or logic-driven output enable signals
·Two global clock signals with optional inversion
·Enhanced interconnect resources for improved routability
·Programmable output slew-rate control

应用 Application

计算机和计算机周边

简介

EPM7064STC44-10N属于集成电路（IC）的CPLD（复杂可编程逻辑器件）。由制造生产的EPM7064STC44-10NCPLD（复杂可编程逻辑器件）CPLD 是用于执行逻辑运算和信息处理的用户可配置集成电路产品；与 PLD 或 PAL 器件相比，这些器件具有更高级别的功能（即更多的逻辑门），但低于 FPGA。CPLD 通常包含非易失性配置存储器，支持直接在器件上存储和保留用户所需的配置，并在器件断电时仍可保留这些信息。