EPM7064AE中文资料阿尔特数据手册PDF规格书
EPM7064AE规格书详情
General Description
MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.
Features...
■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
■ Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages
■ Supports hot-socketing in MAX 7000AE devices
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ PCI-compatible
■ Bus-friendly architecture, including programmable slew-rate control
■ Open-drain output option
■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls
■ Programmable power-up states for macrocell registers in MAX 7000AE devices
■ Programmable power-saving mode for 50 or greater power reduction in each macrocell
■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ 6 to 10 pin- or logic-driven output enable signals
■ Two global clock signals with optional inversion
■ Enhanced interconnect resources for improved routability
■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
■ Programmable output slew-rate control
■ Programmable ground pins
产品属性
- 产品编号:
EPM7064AELC44-4
- 制造商:
Intel
- 类别:
集成电路(IC) > CPLD(复杂可编程逻辑器件)
- 系列:
MAX® 7000A
- 包装:
托盘
- 可编程类型:
系统内可编程
- 供电电压 - 内部:
3V ~ 3.6V
- 工作温度:
0°C ~ 70°C(TA)
- 安装类型:
表面贴装型
- 封装/外壳:
44-LCC(J 形引线)
- 供应商器件封装:
44-PLCC(16.59x16.59)
- 描述:
IC CPLD 64MC 4.5NS 44PLCC
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
ALTERA |
23+ |
QFP |
7000 |
绝对全新原装!现货!特价!请放心订购! |
询价 | ||
ALT |
640 |
询价 | |||||
ALTERA |
23+ |
QFP |
66800 |
现货正品专供军研究院 |
询价 | ||
ALTERA |
2022 |
QFP100 |
5280 |
原厂原装正品,价格超越代理 |
询价 | ||
ALTERA |
2021+ |
TQFP100 |
6031 |
百分百原装正品 |
询价 | ||
ALTERA |
19+ |
QFP |
24642 |
原厂代理渠道,每一颗芯片都可追溯原厂; |
询价 | ||
ALTERA |
22+ |
TQFP1010 |
2679 |
原装优势!绝对公司现货!可长期供货! |
询价 | ||
ALTERA |
23+ |
原厂原包 |
19960 |
只做进口原装 终端工厂免费送样 |
询价 | ||
ALTERA |
22+ |
BGA |
2000 |
进口原装!现货库存 |
询价 | ||
LT/凌特 |
1950+ |
QFP100 |
4856 |
只做原装正品现货!或订货假一赔十! |
询价 |