EPM5064JC-1中文资料阿尔特数据手册PDF规格书

General Description

The MAX 5000 family combines innovative architecture and advanced process technologies to offer optimum performance, flexibility, and the highest logic-to-pin ratio of any general-purpose programmable logic device (PLD) family. The MAX 5000 family provides 600 to 3,750 usable gates, pin-to-pin delays as fast as 15 ns, and counter frequencies of up to 83.3 MHz.

Features...

■ Advanced Multiple Array MatriX (MAX) 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

■ Complete family of high-performance, erasable CMOS EPROM EPLDs for designs ranging from fast 28-pin address decoders to 100-pin LSI custom peripherals

■ 600 to 3,750 usable gates (see Table 1)

■ Fast, 15-ns combinatorial delays and 83.3-MHz counter frequencies

■ Configurable expander product-term distribution allowing more than 32 product terms in a single macrocell

■ 28 to 100 pins available in DIP, J-lead, PGA, SOIC, and QFP packages

■ Programmable registers providing D, T, JK, and SR flipflop functionality with individual clear, preset, and clock controls

■ Programmable security bit for protection of proprietary designs

■ Software design support featuring Altera’s MAX+PLUS II development system on 486- or Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700, and IBM RISC System/6000 workstations

■ Programming support with Altera’s Master Programming Unit (MPU) or programming hardware from other manufacturers

■ Additional design entry and simulation support provided by EDIF, LPM, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Data I/O, Exemplar, Mentor Graphics, MINC, OrCAD, Synopsys, VeriBest, and Viewlogic