Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

文件：1.35316 Mbytes 页数：104 Pages

Altera

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Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

文件：1.35316 Mbytes 页数：104 Pages

Altera

阿尔特

Cyclone FPGA Family Data Sheet

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

文件：1.35316 Mbytes 页数：104 Pages

Altera

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Supports configuration through low-cost serial configuration device

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

文件：706.63 Kbytes 页数：106 Pages

Altera

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Cyclone FPGA Family

文件：1.14233 Mbytes 页数：94 Pages

Altera

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Cyclone FPGA Family

文件：1.14233 Mbytes 页数：94 Pages

Altera

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Cyclone FPGA Family

文件：1.14233 Mbytes 页数：94 Pages

Altera

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EP1C6Q240C6N - 芯片, FPGA, CYCLONE, 5980单元, 240PQFP

The EP1C6Q240C6N is a Cyclone® FPGA based on a 1.5V, 0.13µm features all-layer copper SRAM process with densities up to 5980 logic elements (LEs) and up to 92160-bits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM a ·Supports configuration through low-cost serial configuration device\n·Supports for LVTTL, LVCMOS, SSTL-2 and SSTL-3 I/O standards\n·High-speed (640Mbps) LVDS I/O support\n·Low-speed (311Mbps) LVDS I/O support\n·311Mbps RSDS I/O support\n·Up to two PLLs per device provide clock multiplication and ph;

Intel

英特尔

EP1C6Q240C8N - 芯片, FPGA, CYCLONE, 5980单元, 240PQFP

Intel

英特尔

Package：240-BFQFP；包装：托盘 类别：集成电路（IC） FPGA（现场可编程门阵列） 描述：IC FPGA 185 I/O 240QFP

Intel

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